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PRELIMINARY
CY9C62256
32K x 8 Magnetic Nonvolatile CMOS RAM
Features
* 100% form, fit, function-compatible with 32K x 8 micropower SRAM (CY62256) -- Fast Read and Write access: 70 ns -- Voltage range: 4.5V-5.5V operation -- Low power: 330 mW Active; 495 W standby -- Easy memory expansion with CE and OE features -- TTL-compatible inputs and outputs -- Automatic power-down when deselected * Replaces 32K x 8 Battery Backed (BB)SRAM, SRAM, EEPROM, FeRAM or Flash memory * Data is automatically Write protected during power loss * Write Cycles Endurance: > 1015 cycles * Data Retention: > 10 Years * Shielded from external magnetic fields * Extra 64 Bytes for device identification and tracking * Temperature ranges -- Commercial: 0C to 70C -- Industrial: - 40C to 85C * JEDEC STD 28-pin DIP (600-mil), 28-pin (300-mil) SOIC, and 28-pin TSOP-1 packages. Also available in 450-mil wide (300-mil body width) 28-pin narrow SOIC.
Functional Description
The CY9C62256 is a high-performance CMOS nonvolatile RAM employing an advanced magnetic RAM (MRAM) process. An MRAM is nonvolatile memory that operates as a fast read and write RAM. It provides data retention for more than ten years while eliminating the reliability concerns, functional disadvantages and system design complexities of battery-backed SRAM, EEPROM, Flash and FeRAM. Its fast writes and high write cycle endurance makes it superior to other types of nonvolatile memory. The CY9C62256 operates very similarly to SRAM devices. Memory read and write cycles require equal times. The MRAM memory is nonvolatile due to its unique magnetic process. Unlike BBSRAM, the CY9C62256 is truly a monolithic nonvolatile memory. It provides the same functional benefits of a fast write without the serious disadvantages associated with modules and batteries or hybrid memory solutions. These capabilities make the CY9C62256 ideal for nonvolatile memory applications requiring frequent or rapid writes in a bytewide environment. The CY9C62256 is offered in both commercial and industrial temperature ranges.
Logic Block Diagram
Pin Configurations
SOIC/DIP Top View A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 I/O0 I/O1 I/O2 GND OE A1 A2 A3 A4 WE VCC A5 A6 A7 A8 A9 A10 A11
22 23 24 25 26 27 28 1 2 3 4 5 6 7
INPUTBUFFER A11 A10 A9 A8 A7 A6 A3 A2 A1 CE WE OE A5 A4 A 14 A 13 A12 A0 ROW DECODER
I/O0 I/O1 SENSE AMPS
Silicon Sig. 512x512 Y ARRA
I/O2 I/O3
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VCC WE A4 A3 A2 A1 OE A0 CE I/O7 I/O6 I/O5 I/O4 I/O3
21 20 19 18 17 16 15 14 13 12 11 10 9 8
I/O4 I/O5
COLUMN DECODER
POWER
DOWN & WRITE PROTECT
I/O6 I/O7
TSOP I Top View (not to scale)
A0 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A14 A13 A12
Cypress Semiconductor Corporation Document #: 38-15001 Rev. *E
*
3901 North First Street
*
San Jose, CA 95134 * 408-943-2600 Revised November 15, 2004
PRELIMINARY
Overview
The CY9C62256 is a byte wide MRAM memory. The memory array is logically organized as 32,768 x 8 and is accessed using an industry standard parallel asynchronous SRAM-like interface. The CY9C62256 is inherently nonvolatile and offers write protect during sudden power loss. Functional operation of the MRAM is similar to SRAM-type devices, otherwise. Memory Architecture Users access 32,768 memory locations each with eight data bits through a parallel interface. Internally, the memory array is organized into eight blocks of 512 rows x 64 columns each. The access and cycle time are the same for read and write memory operations. Unlike an EEPROM or Flash, it is not necessary to poll the device for a ready condition since writes occur at bus speed. Memory Operation The CY9C62256 is designed to operate in a manner similar to other bytewide memory products. For users familiar with BBSRAM, the MRAM performance is superior. For users familiar with EEPROM, Flash and FeRAM, the obvious differences result from higher write performance of MRAM technology and much higher write endurance. All memory array bits are set to logic "1" at the time of shipment. Read Operation A read cycle begins whenever WE (Write Enable bar) is inactive (HIGH) and CE (Chip Enable bar) and OE (Output Enable bar) are active LOW. The unique address specified by the 15 address inputs (A0-A14) defines which of the 32,768 bytes of data is to be accessed. Valid data will be available at the eight output pins within tAA (access time) after the last address input is stable, providing that CE and OE access times are also satisfied. If CE and OE access times are not satisfied then the data access must be measured from the later-occurring signal (CE or OE) and the limiting parameter is either tACE for CE or tDOE for the OE rather than address access. Write Cycle The CY9C62256 initiates a write cycle whenever the WE and CE signals are active (LOW) after address inputs are stable. The later occurring falling edge of CE or WE will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE. All address inputs must be kept valid throughout the write cycle. The OE control signal should be kept inactive (HIGH) during write cycles to avoid bus contention. However, if the output drivers are enabled (CE and OE active) WE will disable the outputs in tHZWE from the WE falling edge. Unlike other nonvolatile memory technologies, there is no write delay with MRAM. The entire memory operation occurs in a single bus cycle. Therefore, any operation including read or write can occur immediately following a write. Data Polling, a technique used with EEPROMs to determine if the write is complete is unnecessary. Page write, a technique used to enhance EEPROM write performance is also unnecessary because of inherently fast write cycle time for MRAM. The total Write time for the entire 256K array is 2.3 ms. Document #: 38-15001 Rev. *E
CY9C62256
Write Inhibit and Data Retention Mode This feature protects against the inadvertent write. The CY9C62256 provides full functional capability for VCC greater than 4.5V and write protects the device below 4.0V. Data is maintained in the absence of VCC. During the power-up, normal operation can resume 20 s after VPFD is reached. Refer to page 8 for details. Sudden Power Loss--"Brown Out" The nonvolatile RAM constantly monitors VCC. Should the supply voltage decay below the operating range, the CY9C62256 automatically write-protects itself, all inputs become don't care, and all outputs become high-impedance. Refer to page 8 for details. Silicon Signature/Device ID An extra 64 bytes of MRAM are available to the user for Device ID. By raising A9 to VCC + 2.0V and by using address locations 00(Hex) to 3F(Hex) on address pins A7, A6, A14, A13, A12 and A0 (MSB to LSB) respectively, the additional Bytes may be accessed in the same manner as the regular memory array, with 140 ns access time. Dropping A9 from input high (VCC + 2.0V) to < VCC returns the device to normal operation after 140-ns delay. Address (MSB to LSB) A7 A6 A14 A13 A12 A0 00h 01h 02h - 3Fh Description Manufacturer ID Device ID User Space ID 34h 40h 62 Bytes
All User Space bits above are set to logic "1" at the time of shipment. Magnetic Shielding CY9C62256 is protected from external magnetic fields through the application of a "magnetic shield" that covers the entire memory array. Applications Battery-Backed SRAM (BB SRAM) Replacement CY9C62256 is designed to replace (plug and play) existing BBSRAM while eliminating the need for battery and VCC monitor IC, reducing cost and board space and improving system reliability. The cost associated with multiple components and assemblies and manufacturing overhead associated with battery-backed SRAM is eliminated by using monolithic MRAM. CY9C62256 eliminates multiple assemblies, connectors, modules, field maintenance and environmental issues common with BB SRAM. MRAM is a true nonvolatile RAM with high performance, high endurance, and data retention. Battery-backed SRAMs are forced to monitor VCC in order to switch to the backup battery. Users that are modifying existing designs to use MRAM in place of BB SRAM, can eliminate the VCC controller IC along with the battery. MRAM performs this function on chip. Cost: The cost of both the component and manufacturing overhead of battery-backed SRAM is high. In addition, there is a built in rework step required for battery attachment in case Page 2 of 11
PRELIMINARY
of surface mount assembly. This can be eliminated with MRAM. In case of DIP battery backed modules, the assembly techniques are constrained to through-hole assembly and board wash using no water. System Reliability: Battery-backed SRAM is inherently vulnerable to shock and vibration. In addition, a negative voltage, even a momentary undershoot, on any pin of a battery-backed SRAM can cause data loss. The negative voltage causes current to be drawn directly from the battery, weakens the battery, and reduces its capacity over time. In general, there is no way to monitor the lost battery capacity. MRAM guarantees reliable operation across the voltage range with inherent nonvolatility. Space: Battery-backed SRAM in DIP modules takes up board space height and dictates through-hole assembly. MRAM is offered in surface mount as well as DIP packages. Field Maintenance: Batteries must eventually be replaced and this creates an inherent maintenance problem. Despite projections of long life, it is difficult to know how long a battery will last, considering all the factors that degrade them. Environmental: Lithium batteries are a potential disposal burden and considered a fire hazard. MRAM eliminates all such issues through a truly monolithic nonvolatile solution. Users replacing battery-backed SRAMs with integrated Real Time Clock (RTC) in the same package may need to move RTC function to a different location within the system. EEPROM Replacement CY9C62256 can also replace EEPROM in current applications. CY9C62256 is pinout and functionally compatible to
CY9C62256
bytewide EEPROM, however it does not need data-bar polling, page write and hardware write protect due to its fast write and inadvertent write protect features. Users replacing EEPROMs with MRAM can eliminate the page mode operation and simplify to standard asynchronous write. Additionally, data-bar polling can be eliminated, since every byte write is completed within same cycle. All writes are completed within 70 ns. FeRAM Replacement FeRAM requires addresses to be latched on falling edge of CE, which adds to system overhead in managing the CE and latching function. MRAM eliminates this overhead by offering a simple asynchronous SRAM interface. Users replacing FeRAM can simplify their address decoding since CE does not need to be driven active and then inactive for each address. This overhead is eliminated when using MRAM. Secondly, MRAM read is nondestructive and no precharge cycle is required like the one used with FeRAM.This has no apparent impact to the design, however the read cycle time can now see immediate improvement equal to the precharge time. Boot-up PROM (EPROM, PROM) Function Replacement The CY9C62256 can be accessed like an EPROM or PROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. MRAM may be used to accomplish system boot up function using this condition.
Document #: 38-15001 Rev. *E
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PRELIMINARY
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................... -40C to +85C Supply Voltage to Ground Potential (Pin 28 to Pin 14) ........................................... -0.5V to +7.0V DC Voltage Applied to Outputs in High-Z State[1] ....................................-0.5V to VCC + 0.5V DC Input Voltage[1] .................................-0.5V to VCC + 0.5V
CY9C62256
except in case of Super Voltage pin (A9) while accessing 64 device ID and Silicon signature Bytes.........-0.5V to VCC + 2.5V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage ........................................> 2001V (per MIL-STD-883, Method 3015) Latch-up Current..................................................... > 200 mA Maximum Exposure to Magnetic Field @ Device Package[2,3] ............................................ < 20 Oe
Operating Range
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VCC 5V 10% 5V 10%
Electrical Characteristics Over the Operating Range
CY9C62256-70 Parameter VOH VOL VIH VIL IIX[4] IOZ ICC ISB1 ISB2 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current VCC Operating Supply Current Automatic CE Power-down Current-- TTL Inputs Automatic CE Power-down Current-- CMOS Inputs GND < VI < VCC GND < VO < VCC, Output Disabled VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Max. VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX Max. VCC, CE > VCC - 0.3V VIN > VCC - 0.3V or VIN < 0.3V, f = 0 Test Conditions VCC = Min., IOH = -1.0 mA VCC = Min., IOL = 2.1 mA 2.2 -0.5[1] -0.5 -0.5 Min. 2.4 0.4 VCC + 0.5V 0.8 +0.5 +0.5 60 Typ.[5] Max. Unit V V V V A A mA
500
A
90
A
Capacitance[6]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. 6 8 Unit pF pF
Notes: 1. VIL (min.) = -2.0V for pulse duration of 20 ns. 2. Magnetic field exposure is highly dependent on the distance from the magnetic field source. The magnetic field falls off as 1/R squared, where R is the distance from the magnetic source. 3. Exposure beyond this level may cause loss of data. 4. IIX during access to 64 device ID and silicon signature bytes with super voltage pin at VCC + 2.0V will be 100 A max. 5. Typical specifications are the mean values measured over a large sample size across normal production process variations and are taken at nominal conditions (TA = 25C, VCC). Parameters are guaranteed by design and characterization, and not 100% tested. 6. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-15001 Rev. *E
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PRELIMINARY
AC Test Loads and Waveforms
5V OUTPUT 100 pF INCLUDING JIG AND SCOPE R2 990 R1 1800 R1 1800 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE R2 990 3.0V GND 10%
CY9C62256
ALL INPUT PULSES 90% 90% 10% < 5 ns THEVENIN EQUIVALENT 639 1.77V
(a)
(b)
< 5 ns Equivalent to: OUTPUT
Switching Characteristics Over the Operating Range[7]
CY9C62256-70 Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD Write Cycle[10,11] tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE Write Cycle Time CE LOW to Write End Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width Data Set-up to Write End Data Hold from Write End WE LOW to High Z[8, 9] 5 WE HIGH to Low Z[8] 70 60 60 0 0 50 30 0 25 ns ns ns ns ns ns ns ns ns ns Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z[8] OE HIGH to High Z[8,9] CE LOW to Low Z[8] CE HIGH to High Z[8,9] 0 70 CE LOW to Power-up CE HIGH to Power-down 5 25 5 25 5 70 35 70 70 ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. Unit
Notes: 7. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 100-pF load capacitance. 8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 9. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage. 10. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 11. The minimum write pulse width for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 38-15001 Rev. *E
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PRELIMINARY
Switching Waveforms
Read Cycle No. 1 [12, 13]
tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
CY9C62256
Read Cycle No. 2 [13,14]
CE tACE OE tDOE DATA OUT tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50%
tRC
tHZOE tHZCE DATA VALID tPD
HIGH IMPEDANCE
ICC 50% ISB
Write Cycle No. 1 (WE Controlled)
ADDRESS
[10,15,16]
tWC
CE tAW WE tSA tPWE tHA
OE tSD DATA I/O NOTE 17 tHZOE
Notes: 12. Device is continuously selected. OE, CE = VIL. 13. WE is HIGH for read cycle. 14. Address valid prior to or coincident with CE transition LOW. 15. Data I/O is high impedance if OE = VIH. 16. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 17. During this period, the I/Os are in output state and input signals should not be applied.
tHD
DATA IN VALID
Document #: 38-15001 Rev. *E
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PRELIMINARY
Switching Waveforms (continued)
Write Cycle No. 2 (CE Controlled)
ADDRESS CE tSA tAW WE tSD DATA I/O
[11,16] [10,15,16]
CY9C62256
tWC
tSCE tHA
tHD
DATA IN VALID
Write Cycle No. 3 (WE Controlled, OE LOW)
tWC ADDRESS
CE tAW WE tSA tHA
tSD DATA I/O NOTE 17 tHZWE DATA IN VALID
tHD
tLZWE
Truth Table
CE H L L L X WE X H L H X OE X L X H X VCC 4.5V-5.5V 4.5V-5.5V 4.5V-5.5V 4.5V-5.5V <4.0V Inputs/Outputs High Z Data Out Data In High Z Inputs = X, Outputs = Hi-Z Read Write Deselect, Output Disabled Write Inhibit Mode Deselect/Power-down Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC)
Document #: 38-15001 Rev. *E
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PRELIMINARY
Power-down/-up Mode AC Waveforms Parameter VPFD tF[18] tFB tR tWP tREC Description Power-fail Deselect Voltage VPFD (max.) to VPFD (min.) VCC Fall Time VPFD (min.) to VSS VCC Fall Time VSS to VPFD (max.) Rise Time Write Protect Time On VCC = VPFD (typ) VPFD (max.) to Inputs Recognized
tF Vcc VPFD (max) VPFD (min)
CY9C62256
Typ. 4.35 Max. 4.5 Unit V s s s 20 500 s s
Min. 4.2 100 50 20
VPFD (typ)
tFB
tR
tR tREC
tWP
INPUTS
RECOGNIZED
DON'T CARE
RECOGNIZED
OUTPUTS
VALID
HIGH-Z
VALID
Ordering Information
Speed (ns) 70 Ordering Code CY9C62256-70SC CY9C62256-70SI CY9C62256-70SNC CY9C62256-70SNI CY9C62256-70ZC CY9C62256-70ZI CY9C62256-70PC CY9C62256-70PI Package Name S21 S21 SN28 SN28 Z28 Z28 P15 P15 Package Type 28-lead (300-mil) Molded SOIC 28-lead (300-mil) Molded SOIC 28-lead (300-mil) Narrow Body SOIC 28-lead (300-mil) Narrow Body SOIC 28-lead Thin Small Outline Package 28-lead Thin Small Outline Package 28-lead (600-mil) Molded DIP 28-lead (600-mil) Molded DIP Operating Range Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial
Note: 18. VPFD (max.) to VPFD (min.) fall time of less than tF may result in deselection/ write protection not occurring until 20 s after VCC passes VPFD (min.).
Document #: 38-15001 Rev. *E
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PRELIMINARY
Package Diagrams
28-lead (600-mil) Molded DIP P15
CY9C62256
51-85017-*A
28-Lead (300-Mil) Molded SOIC S21
PIN 1 ID
(
)
14
1
DIMENSIONS IN INCHES[MM] MAX.
0.394[10.01] 0.291[7.39] 0.300[7.62] 0.419[10.64] *
MIN.
MIN. MAX.
REFERENCE JEDEC MO-119 PACKAGE WEIGHT 0.85gms
PART # SZ28.3 LEAD FREE PKG.
15
28
0.026[0.66] 0.032[0.81]
PART # S28.3 STANDARD PKG. SZ28.3 LEAD FREE PKG.
0.697[17.70] 0.713[18.11]
SEATING PLANE
0.092[2.33] 0.105[2.67] 0.004[0.10] 0.050[1.27] TYP. 0.013[0.33] 0.019[0.48] 0.004[0.10] 0.0118[0.30] * 0.015[0.38] 0.050[1.27] 0.0091[0.23] 0.0125[3.17] *
51-85026-*C
Document #: 38-15001 Rev. *E
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PRELIMINARY
Package Diagrams (continued)
28-lead Thin Small Outline Package Type 1 (8 x 13.4 mm) Z28
CY9C62256
51-85071-*G
450-mil Wide (300-mil Body Width) 28-pin Narrow SOIC (SN28)
PIN 1 ID
DIMENSIONS IN INCHES
OMEDATA CSPI
MIN. MAX.
0.390 0.420
0.291 0.300
0.463 0.477 0.026 0.032 0.014 0.020 0.015 0.020
DETAIL "B"
DETAIL "A"
SEATING PLANE
0.390 0.420 B
0.702 0.710
0.094 0.110
A
0.004 0.002 0.014 0.020 0.042
0.050 TYP.
0.008 0.012
51-85092-*B
All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-15001 Rev. *E Page 10 of 11
(c) Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
PRELIMINARY
Document History Page
Document Title: CY9C62256 32K x 8 Magnetic Nonvolatile CMOS RAM Document Number: 38-15001 REV. ** *A *B *C *D *E ECN NO. 115831 116770 117612 208424 227582 285756 Issue Date 05/29/02 07/25/02 07/26/02 SEE ECN SEE ECN SEE ECN Orig. of Change NBP NBP LJN NBP NBP NBP New data sheet Add state of memory bits at the time of shipment Description of Change
CY9C62256
Minor Change needed to change footer from 38-15003 to 38-15001 Icc, Isb1, Isb2, Non-Operating Shielding Specification, Condition to emulate Boot PROM functionality Changed Magnetic Shielding Specification Added SNC 28-pin SOIC package and Changed VPFD and tWP specification
Document #: 38-15001 Rev. *E
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